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CD40108BMS
December 1992
CMOS 4 x 4 Multiport Register
Description
The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-impedance state. The high-impedance third state provides the outputs with the capability of being connected to the bus lines in a bus-organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input. The CD40108BMS is supplied in these 24-lead outline packages: Braze Seal DIP Ceramic Flatpack H4V H4P
Features
* High Voltage Type (20V Rating) * Four 4-Bit Registers * One Input and Two Output Buses * Unlimited Expansion in Bit and Word Directions * Data Lines have latched Inputs * 3-State Outputs * Separate Control of Each Bus, Allowing Simultaneous Independent Reading of Any of Four Registers on Bus A and Bus B and Independent Writing Into Any of the Four Registers * CD40108BMS is Pin-Compatible with Industry Type MC14580 * Standardized Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Scratch-Pad Memories * Arithmetic Units * Data Storage
Pinout
CD40108BMS TOP VIEW
Q3 B 1 Q2 B 2 3-STATE A 3 Q0 A 4 Q1 A 5 Q2 A 6 Q3 A 7 WRITE 0 8 WRITE 1 9 READ 1B 10 READ 0B 11 VSS 12 24 VDD 23 Q1 B 22 Q0 B 21 3-STATE B 20 D0 19 D1 18 D2 17 D3 16 CLOCK 15 WRITE ENABLE 14 READ 1A 13 READ 0A
Functional Diagram
WRITE ENABLE D0 DATA INPUTS D1 D2 D3 WRITE 0 WRITE 1 READ 1A READ 0A READ 1B READ 0B VDD = 24 VSS = 12 20 19 18 17 8 9 14 13 10 11 16 CLOCK 21 3-STATE B 22 23 2 1 Q0 Q1 Q2 Q3 WORD B OUTPUT 3-STATE A 15 3 4 5 6 7 Q0 Q1 Q2 Q3 WORD A OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3356
7-25
Specifications CD40108BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V A A A A A A MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
+25oC, +125oC, -55oC 14.95
VOH > VOL < VDD/2 VDD/2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-26
Specifications CD40108BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 1.5 1.11 MAX 720 972 600 810 200 270 260 351 200 270 UNITS ns ns ns ns ns ns ns ns ns ns MHz MHz
PARAMETER Propagation Delay Clock or Write Enable to Q Propagation Delay Read or Write Address to Q Propagation Delay 3State Disable Delay Time Propagation Delay 3State Disable Delay Time Transition Time
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPZH TPHZ TPZL TPLZ TTHL TTLH FCL
CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2)
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
Maximum Clock Input Frequency NOTES:
+25oC +125oC, -55oC
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
oC o o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 -
MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA
+125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
7-27
Specifications CD40108BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH10 CONDITIONS VDD = 10V, VOUT = 9.5V NOTES 1, 2 TEMPERATURE +125oC -55 C Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55 Input Voltage Low Input Voltage High Propagation Delay Clock or Write Enable to Q Propagation Delay Read or Write Address to Q Propagation Delay 3-State Disable Delay Time Propagation Delay 3-State Disable Delay Time Transition Time VIL VIH TPLH1 TPHL1 TPHL2 TPLH2 TPZH TPHZ TPZL TPLZ TTLH TTHL FCL VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time Write Enable to Clock Minimum Data Setup Time Write Address to Clock Clock Rise and Fall Time TS VDD = 5V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Minimum Hold Time Data to Clock TH VDD = 5V VDD = 10V VDD = 15V Hold Time Write Enable to Clock TH VDD = 5V VDD = 10V VDD = 15V Write Address to Clock TH VDD = 5V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
oC o
MIN 7 3.5 4.5 0 0 0 250 100 70 250 100 70 220 100 80 -
MAX -0.9 -1.6 -2.4 -4.2 3 280 200 240 170 100 80 120 100 100 80 -
UNITS mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25
oC o o
Maximum Clock Input Frequency Minimum Data Setup Time Data to Clock
+25oC +25 C +25
oC o
+25oC +25
oC
+25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
15 5 5
ns ns ns ns ns ns
270 130 80 330 140 90
ns ns ns ns ns ns
7-28
Specifications CD40108BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width Clock or Write Enable Minimum Clock Pulse Width Write Address SYMBOL TW CONDITIONS VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. CIN Any Input NOTES 3 3 3 3 3 3 1, 2 TEMPERATURE +25oC +25 C +25oC +25
oC o
MIN -
MAX 350 130 90 300 150 90 7.5
UNITS ns ns ns ns ns ns pF
+25oC +25oC +25
oC
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25 C +25 C +25oC +25 C +25oC
o o o
MIN -2.8 0.2 VOH > VDD/2 -
MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit
UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) MIL-STD-883 METHOD 100% 5004 GROUP A SUBGROUPS 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A
7-29
Specifications CD40108BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 1 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic BurnIn (Note 1) Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1, 2, 4 - 7, 22, 23 1, 2, 4 - 7, 22, 23 1, 2, 4 - 7, 22, 23 GROUND 3, 8 - 12 2 2 2 VDD 24 3, 8 - 11, 13 - 21, 24 3, 15, 16, 21, 24 3, 8 - 11, 13 - 21, 24 1, 2, 4 - 7, 22, 23 8, 11, 14, 19, 20 9, 10, 13, 17, 18 9V -0.5V 50kHz 25kHz
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
30
CD40108BMS Block Diagram
W0 CL WE W1 R0A R1A R0B R1B
DEC
DEC
DEC ENABLE A Q0 A Q1 A Q2 A WORD A OUTPUT
D0 DATA INPUT D1 D2 D3
4X4 MEMORY
Q3 A
Q0 B Q1 B Q2 B Q3 B ENABLE B WORD B OUTPUT
FIGURE 1. TRUTH TABLE WRITE WRITE CLOCK ENABLE 1 1 1 X X 1 0 X X X 1 = High Level S1 S1 X 0 0 X X WRITE 0 S2 S2 X 0 0 X X READ 1A S1 S1 X 0 0 1 X READ 0A S2 S2 X 1 1 0 X READ 1B S1 S1 X 1 1 0 X READ 0B S2 S2 X 0 0 1 X ENABLE ENABLE A B 1 1 0 1 1 1 1 1 1 0 1 1 1 1 DN 1 0 X QnA 1 0 Z QnB 1 0 Z Word 2 out Word 2 out Word 1 out NC
Dn to word Word 1 0 out Word 0 Word 1 not altered out X X Word 2 out NC
0 = Low Level
X = Don't Care
Z = High Impedance
S! and S2 refer to input states of either 1 or 0
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
FIGURE 3. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
7-31
CD40108BMS Typical Performance Characteristics
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
(Continued)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30 -35
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
450 SUPPLY VOLTAGE (VDD) = 5V 375 300 225 10V 150 75 0 0 10 20 30 40 50 60 70 80 90 100 15V
TRANSITION TIME (tTHL, tTLH) (ns)
525
AMBIENT TEMPERATURE (TA) = +25oC
200
150
SUPPLY VOLTAGE (VDD) = 5V
100 10V 50 15V
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CL OR WE TO Q)
106 8
6 4 2 8 6 4
FIGURE 7. TYPICAL TRANSISTION TIME AS A FUNCTION OF LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V
POWER DISSIPATION (PD) (W)
105
104
2 8 6 4
10V 10V 5V
103
2 8 6 4
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
102
2
1
103 10 102 INPUT FREQUENCY (fI) (kHz)
104
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
7-32
Schematic Diagram
*
C
13
R0A
*
14
R1A
*
11
R0B
*
10
R1B 3-STATE
*A ENABLE
3
C
*CLOCK *WRITE
ENABLE
16
15
4
Q0A
*W0 *W1
8 A 9 C D W B QA QB A D W B QA QB A D W B QA QB A D W B QA QB 6 Q2A 5 Q1A
CD40108BMS
*D0
20
p n C C D p n C C W A B QA QB A D W B QA QB A D W B QA QB A D W B QA QB
7
Q3A
FIGURE 9.
7-33
22
Q0B
*D1
19
p n C C p n C C D W A B QA QB A D W B QA QB A D W B QA QB A D W B QA QB
23
Q1B
2
Q2B
*D2
18
p n C C p n C C A D W B QA QB A D W B QA QB A D W B QA QB A D W B QA QB
1
Q3B
*D3
17
p n C C p n C 21 3-STATE *B ENABLE
*ALL INPUTS PROTECTED BY
COS/MOS INPUT PROTECTION NETWORK
CD40108BMS Schematic Diagram
(Continued)
A D p n p n QA
ENABLE
VDD
VDD p n W VSS p n B QB
INPUT
OUTPUT
VSS
DETAIL OF MEMORY CELL
DETAIL OF 3-STATE OUTPUTS
FIGURE 9. (Continued)
trCL CL tH(D) tS(D) Dn tH(WE) WE tS(WE) tH(WA) tS(WA) tW(WA) tfCL tW(CL)
WA
RA tPHL tPLH Qn tTLH tTHL tPHL tPLH tPHL tPLH
FIGURE 10. TIMING DIAGRAM
0.1 F ID CL 1 2 CL CL 3 4 5 CL CL CL 6 7 8 9 10 PULSE GEN. 3 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PULSE GEN. 1 REPETITIVE WAVEFORMS PULSE GEN. 2 P.G. 3 Qn A, B CL P.G. 2 CL P.G. 1 (FI) VDD 500 F
FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS
7-34
CD40108BMS
1 2 Q 3 4 5 1k TO ANY OUTPUT 50pF 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13 D
PULSE GEN. 2 P.G. 1 P.G. 2 ENABLE INPUT 50% tPLZ PULSE GEN. 1 Q OUTPUTS tPHZ 10% 90% CL ENABLE VDD 50% VSS tPZL VDD 90% VOL VOH 10% VSS tPZH
CHAR tPHZ tPZH tPLZ tPZL
TEST VOLTAGE AT D AT Q VDD VSS VDD VSS VSS VDD VSS VDD
FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-35

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